EP1S40F1020I6

Product Summary

The EP1S40F1020I6 is a FPGA based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities of up to 79,040 logic elements (LEs) and up to 7.5 Mbits of RAM. The EP1S40F1020I6 offers up to 22 digital signal processing (DSP) blocks with up to 176 (9-bit × 9-bit) embedded multipliers, optimized for DSP applications that enable efficient implementation of high-performance filters and multipliers. The EP1S40F1020I6 supports various I/O standards and also offer a complete clock management solution with its hierarchical clock structure with up to 420-MHz performance and up to 12 phase-locked loops (PLLs).

Parametrics

EP1S40F1020I6 absolute maximum ratings: (1)VCCINT, Supply voltage With respect to ground: –0.5 to 2.4 V; (2)VCCIO: –0.5 to 4.6 V; (3)VI, DC input voltage: –0.5 to 4.6 V; (4)IOUT, DC output current, per pin: –25 to 40 mA; (5)TSTG, Storage temperature No bias: –65 to 150℃; (6)TJ, Junction temperature BGA packages under bias: 135℃.

Features

EP1S40F1020I6 features: (1)Support for 133-MHz PCI-X 1.0 in -5 speed-grade devices; (2)Support for 100-MHz PCI-X 1.0 in -6 and faster speed-grade devices; (3)Support for 66-MHz PCI-X 1.0 in -7 speed-grade devices; (4)Support for multiple intellectual property megafunctions from Altera MegaCore functions and Altera Megafunction Partners Program (AMPPSM) megafunctions; (5)Support for remote configuration updates; (6)10,570 to 79,040 LEs; see Table 1–1; (7)Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources; (8)TriMatrixTM memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers; (9)High-speed DSP blocks provide dedicated implementation of multipliers (faster than 300 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters; (10)Up to 16 global clocks with 22 clocking resources per device region; (11)Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switch-over, real-time PLL reconfiguration, and advanced multiplication and phase shifting.

Diagrams