TMS320C6701GJC1671.9V

Product Summary

The TMS320C6701GJC1671.9V is the floating-point DSP in the TMS320C6000 DSP platform. The TMS320C6701GJC1671.9V device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the TMS320C6701GJC1671.9V offers cost-effective solutions to high-performance DSP programming challenges. The TMS320C6701GJC1671.9V possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The TMS320C6701GJC1671.9V can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

Parametrics

TMS320C6701GJC1671.9V absolute maximum ratings: (1)Supply voltage range, CVDD: 0.3 V to 2.3 V; (2)Supply voltage range, DVDD: 0.3 V to 4 V; (3)Input voltage range: 0.3 V to 4 V; (4)Output voltage range: 0.3 V to 4 V; (5)Operating case temperature range, TC (Default): 0℃ to 90℃; (6)(A Version): 40℃ to 105℃; (7)Storage temperature range, Tstg: 55℃ to 150℃.

Features

TMS320C6701GJC1671.9V features: (1)Highest Performance Floating-Point Digital Signal Processor (DSP); (2)VelociTI. Advanced Very Long Instruction Word (VLIW) C67x CPU Core; (3)Instruction Set Features; (4)1M-Bit On-Chip SRAM; (5)32-Bit External Memory Interface (EMIF); (6)Four-Channel Bootloading; (7)16-Bit Host-Port Interface (HPI); (8)Two Multichannel Buffered Serial Ports(McBSPs); (9)Two 32-Bit General-Purpose Timers; (10)Flexible Phase-Locked-Loop (PLL) Clock Generator; (11)IEEE-1149.1 Boundary-Scan-Compatible; (12)352-Pin Ball Grid Array (BGA) Package(GJC Suffix); (13)0.18-μ/5-Level Metal Process CMOS Technology; (14)3.3-V I/Os, 1.8-V Internal (120-, 150-MHz); (15)3.3-V I/Os, 1.9-V Internal (167-MHz Only).

Diagrams